1. Field of the Invention
This invention relates to an image processor and more particularly to an image processor for making continuous-tone image display of a liquid crystal display (LCD) by a digital driver.
2. Description of the Related Art
A method generally called time series operation processing, namely, a method of image processing by assuming a number of frames to be one screen (hereinafter, one unit of the image processing is referred to as a time series information pattern) is known as an image processing method according to conventional examples, especially for making continuous-tone image display of an LCD.
The time series operation processing (FRC) is described with reference to FIG. 1, wherein only red is discussed because green and blue are handled as red is.
A time series arithmetic processing unit according to a conventional example consists of a dot counter 21, a line counter 22, a frame counter 23, a gradation control circuit 24, a selector 25, and an adder 26, as shown in FIG. 1.
In FIG. 1, He is a horizontal synchronizing signal, Ve is a vertical horizontal synchronizing signal, and CKe is a dot clock. Eight bits of source image data corresponding to red are R0 to R7. The 8-bit data is divided into high-order six bits and low-order two bits which are used as data concerning four scales added.
Among the eight data bits R0 to R7, R7 is the most significant bit (MSB) and R0 is the least significant bit (LSB). The high-order six bits R2 to R7 take values 0 to 63 indicating 64 scales, as listed under values a in Table 1. The six bits are input to the adder 26 which then adds 1 to the 6-bit value to generate 6-bit data r2 to r7, as listed under values b in Table 1. Table 1 is a table for comparing values a and b.
TABLE 1 ______________________________________ Value a Value b Val- Val- R7 R6 R5 R4 R3 R2 ue r7 r6 r5 r4 r3 r2 ue ______________________________________ 1 1 1 1 1 1 63 1 1 1 1 1 1 63 1 1 1 1 1 0 62 1 1 1 1 1 1 63 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 0 0 60 1 1 1 1 0 1 61 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 1 0 2 0 0 0 0 1 1 3 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ______________________________________
Next, Ve is fed into the frame counter 23 to generate a signal whose period is twice that of Ve, V0, and a signal whose period is four times that of Ve, V1. Frame numbers 0-3 are determined by the value of V1 and V0, and are repeated together with Ve. A signal whose period is twice that of CKe, C0, and a signal whose period is four times that of CKe, C1, are generated by the dot counter 21 with CKe as a clock like the frame counter 23. Likewise, H0 and H1 are generated by the line counter 22 by using He as a clock.
The gradation control circuit 24 generates a time series information pattern with four frames as one cycle by using 16 dots (horizontal four dots x vertical four dots) as one unit. Next, four scales indicated by the low-order two data bits R0 and R1 are considered and a time series information pattern in response to each scale is considered. 0 or 1 is given to each dot of the time series information pattern (one period or cycle: Horizontal four dots x vertical four dots x four frames) to define the average values of one period so that they become in the gradation order of four scales for each dot. Reduction of flickering is intended according to how to give 0 or 1.
Based on the time series information pattern, a control signal (STR) is generated for the selector 25 to select value a or b. First, a time series information pattern corresponding to the scale indicated by the low-order two data bits R0 and R1 is selected. Next, frames are distinguished from each other by V0 and V1 output from the frame counter 23. Further, a horizontal dot is selected by C0 and C1 output from the dot counter 21 and a vertical dot is selected by H0 and H1 output from the line counter 22. The value of the specified one point becomes the control signal (STR).
The control signal (STR) thus generated controls the selector 25 to output value a when the signal is 0 or value b when 1. Here, the specified one point is noted. The control signal (STR) selectively outputs value a or b, as listed in Table 2, in response to the data number 0-3 specified by the low-order two data bits R0 and R1 and the frame number 0-3. By the fact that value b is provided by adding 1 to value a for the one dot specified by the data number (R0, R1), the average values of four frames become
a+0.25 PA1 a+0.5 PA1 a+0.75
with respect to the data numbers 0 to 3 respectively, as listed in Table 2. This shows that four scales into which gradation is further divided between the scale corresponding to the value a (digital) and the scale corresponding to the value b greater by one than the value a are displayed as averages. Although only red is discussed here, similar processing is performed for green and blue. Table 2 is a table listing the data numbers and the frame numbers by the control signal (STR) and the average values of brightness.
Eight-bit data is compressed into 6-bit data for making continuous-tone image display by the time series operation processing as described above.
TABLE 2 ______________________________________ Values by STR and average values Frame No. Average Data No. 0 1 2 3 value ______________________________________ 0 a a a a a 1 b a a a a + 0.25 2 a b a b a + 0.5 3 a b b b a + 0.75 ______________________________________
In the time series operation processing discussed above, the number of scales is increased by increasing the number of frames per time series information pattern. In the example given above, four frames are considered one screen, in which case continuous-tone image display is enabled having the number of scales about four times that of display where one frame is one screen.
However, since gradation is represented using a number of frames as an image of one unit in the image processing method by the conventional time series operation processing described above, the number of frames of one unit needs to be much increased to increase the number of scales, leading to degradation of the actual frame rate (the number of frames per unit time) and causing images to flicker.
For example, normally 60 frames are displayed a second on an LCD. If the number of frames of one unit in time series operation processing is 16 as an example, the number of scales is remarkably increased to improve the continuous-tone image display capability, but repetitions of about three periods a second are made as an image. In such a degree, the image is recognized as flickering that can be noted by human's eyes.
For this reason, formerly only two to four frames were able to be provided for the number of frames of one time series information pattern unit; therefore, the continuous-tone image display capability was only able to be improved by two to four times at most. It is difficult to make a displayed image approach to the source image.
Also in the aspect of the circuit configuration, a complicated circuit for generating time series information patterns needs to be provided; it is difficult to implement such a circuit configuration.